With the module suggested on this page, it’s roughly a matter of replacing the existing FIFO between Xillybus and the application logic with another FIFO, having a depth measured in Gigabytes.īut it’s a wider issue: In many FPGA applications there’s a need for a plain, standard FIFO that is substantially deeper than possible with the memory resources given by the FPGA itself. However that requires some kind of logic to get the data on and off the DDR memories. As the FPGA boards involved often have DDR RAM memories with a much larger bandwidth capability, it’s appealing to suggest using the DDR memories as the immediate target for the data, and then move the data further to the computer with Xillybus at a slower pace. This module was written in response to repeated request for one-shot data acquisition with Xillybus at bandwidths that are above what Xillybus makes possible (or even the PCIe interface itself).
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